1. Technical Field
The present invention relates to a test apparatus and a test method.
2. Related Art
One known apparatus for testing a device under test such as a semiconductor chip is equipped with a plurality of test circuits. In this case, it is desirable to synchronize the operation of the plurality of test circuits.
Some examples of such a test apparatus are disclosed in WO No. 2003/062843 and Japanese Patent Application Publication No. 2007-52028.
The plurality of test circuits of such a test apparatus operate according to a program or a sequence which are given in advance. The test apparatus synchronizes the operation of the test circuits by synchronization of the start/stop of the execution of such programs.
However, when performing various types of tests, simply synchronizing the execution start of the program in each test circuit is not often enough. For example, there may be cases where it is required to execute the next step in synchronization, on condition that a failure has been detected in a predetermined test circuit. If the size of the test apparatus becomes large in such cases, the synchronization circuit that collects and distributes synchronization signals becomes accordingly large, thereby making the implementation difficult.